The invention relates to a semiconductor device having gate oxides of different thicknesses.
As the size of semiconductor devices, i.e., the channel length of integrated circuit devices, are scaled down, the thickness of the gate oxide layer is also decreased correspondingly. Semiconductor technology has advanced to a point where some devices have very thin gate oxides, e.g., about 60 Angstroms, where high density VLSI circuits are required.
Within such devices, the transistors with very thin gate oxides need to be operated with low voltage, e.g., about 3 volts or less, in order to prevent damages to the gate oxides. This low voltage limitation may not adequate for the input/output (I/O) requirements of the integrated circuit.
Many MOS devices external to the high density integrated circuit operate in a 5 volt regime. In fact, some semiconductor devices requires an even higher voltage, e.g., about 21 volts or more, as a power source or for operation of peripheral circuits. These MOS devices are provided with a longer channel length and thicker gate oxide layer for optimal performance. Accordingly, an effective method of providing gate oxides of different thicknesses is needed for semiconductor devices that are configured to handle two or more voltage levels.